In a multi-chip module (MCM), a matrix of electronic devices, typically chips, are generally mounted on a multi-level ceramic (MLC) carrier. One of the main functions of such an MLC carrier is to interconnect the chips or other electronic devices mounted to the carrier ("top-to-top" connections) and to interconnect such chips to the input-output or I/O connections of the carrier board ("top-to-bottom" connections).
If the number of chips or chip connections increases, there is a corresponding need to increase the number of layers in the MLC carrier. Such additional layers are needed because there is only so much area available on each layer for the lines and vias which are formed within each ceramic level. For example, one typical MLC module uses line widths of approximately four mils (1 mil=0.001 inches=0.0254 mm), with five mils spacing between the lines, and vias occupying about nine mils. The current art with 100 chips on the carrier requires an MLC carrier of more than 50 layers.
For a variety of performance as well as manufacturing reasons, including cost and yield concerns, it is desirable to limit the number of MLC layers. One solution of the current art is to use "thin films," generally made of polyimide, polymeric material, or other organic material having a low dielectric constant and copper wiring. The polyimide-copper thin film generally can have conductive lines and vias patterned on the thin film at a higher density than typical MLC carriers. The finer line widths and via sizes which can be patterned on thin films therefore allow each layer of a thin film to replace many corresponding layers of an MLC carrier. A typical thin film (TF) has a one-mil line width, a one-mil spacing, and one-mil vias; widths can be as small as one-half a mil, that is, about 13 microns. The higher densities made possible by thin film technology contain or reduce the complexity of MLC carriers. Typically, the thin film is secured to one of the planar surfaces of the MLC carrier and appropriate interconnections are made between the opposing, "mating" surfaces of the thin film and the MLC carrier.
The use of thin films also enhances the ability to repair certain defects in the resulting MLC carrier. Furthermore, the polyimide material and copper lines and vias of a thin film interconnect generally produce better electrical performance than the typical MLC carrier. As such, thin film technology has been a critical part of high-performance interconnect carriers for almost all MCMs.
In spite of its importance to MCM performance and manufacturability, thin film processing has traditionally been a painstaking, slow process with an associated long cycle time. Because the MCM generally comprises a ceramic (MLC) carrier with a thin film processed on top of the carrier, the MLC carrier must be built first, before the thin film processing can begin. Under traditional manufacturing techniques, the MLC carrier must have the surface destined to mate with the thin film properly finished and prepared, especially because thin film processing of the MLC carrier requires a substantially flat, smooth, and pin-hole free mating surface.
Another drawback to current thin film manufacturing processes is that, when a thin film is found defective, additional manufacturing steps, including lap and polish, must be undertaken to remove the thin film from the MLC carrier and to prepare the MLC carrier to receive a replacement thin film. Further, large format, multi-up processing of MLCs with thin film is impractical due to the weight and bulk of the ceramic substrates and the unavailability of large-format MLC substrates.
The prior art has attempted to address the aforementioned drawbacks and disadvantages, but has achieved mixed results. For example, in order to reduce thin film processing cycle time and costs, a parallel processing manufacturing technique has been devised. According to this technique, the thin film is processed on a "sacrificial carrier," and is then transferred to the MLC carrier after electrical testing. Parallel processing means that thin film processing can occur separate and apart from the MLC substrate to which the thin film will ultimately be bonded. Parallel processing often also improves the yield of both of the MLC carriers and the thin films, as only those which pass the electrical test will be used together. Furthermore, the use of the sacrificial carrier improves the ability to process thin films in the "multi-up" format.
Although parallel processing may appear to address some of the drawbacks of thin film manufacturing technology, it is nonetheless characterized by several major drawbacks, and is generally less than ideal. One such drawback is, for example, that certain parallel processing techniques often use passive rather than active connections. An example of such a process is found in U.S. Pat. No. 4,812,191 issued to Ho. In such a process, the thin film is formed on an aluminum sacrificial carrier. The thin film is then laminated to an organic board. Connection from thin film to board is made by drilling and through-hole plating. The chip or electronic device is connected by wire bonding to the thin film. It can be appreciated by those skilled in the art that such a connection arrangement is less than ideal, limiting the performance and connection density.
The prior art processes of achieving active via connections with thin film also have drawbacks and disadvantages. In particular, when the thin film has been completely formed on a sacrificial carrier, typically glass according to prior art techniques, the thin film is released from the carrier in a free-standing form by using suitable laser techniques. In techniques disclosed in U.S. Pat. No. 4,812,191; No. 5,170,931; No. 5,258,236; and No. 5,534,094, the thin film is held after release in its free-standing form by a ring or frame which engages the edges of the thin film. The free-standing thin film is then laminated to an MLC carrier or module with its vias aligned with those of the MLC. The via connection between the thin film and the MLC carrier is achieved by gold, thermo-compression bonding.
Many of the drawbacks and disadvantages of this approach relate to the fact that the thin film is released from its sacrificial carrier in a free-standing form before lamination joining with the MLC. When the thin film is thus released, its internal stress generally will cause it to shrink, often by over 0.2% depending on the number of levels of the thin film. The shrinkage of the thin film makes it difficult to align the vias and other electrical connections of the thin film to the corresponding MLC carrier. Such shrinkage, and even distortion, are exacerbated if the thin film is released from its sacrificial carrier too soon in the manufacturing process. The solution of holding the thin film around its edges with a ring or frame after release has the additional disadvantage of reducing the active thin film area.
As a further disadvantage, once the thin film is held in its free-standing form described above, subsequent handling and cleaning of the thin film are difficult. Forces exerted against the thin film while it is being handled or cleaned often result in further distortion of the thin film, rendering its subsequent alignment with the corresponding MLC carrier all the more difficult. Similarly, tests of the thin film when it is in its free-standing form create pressure which may affect not only the results of the tests, but subsequent performance of the thin film itself. Should the thin film become contaminated, it likewise becomes difficult to remove such contamination without applying solution or forces, either of which may damage or distort the thin film.
Gold Compression Bonding
Additional drawbacks to thin film manufacturing techniques of the prior art relate to the use of gold compression bonding. Although reliable, this bonding method takes place at a relatively high temperature, such as 350.degree. C., and relatively high pressure, typically above 200 psi. These high temperatures and pressures may damage and distort the thin film and may also compromise the connections to the thin film.
The high temperature required for this method of joining restricts its use to carriers which can tolerate such temperatures. Because most printed wiring board systems have a maximum operable temperature of 250.degree. C., they cannot receive thin films joined by the gold compression bonding technique. Even when a carrier is used which can tolerate the heat of gold compression bonding, such as an MLC carrier, the high temperature often softens the polyimide material of the thin film, making it more prone to damage and distortion. Further, the high pressures of gold compression bonding often cause distortion in the form of expansion of the thin film. Such expansion often affects the registration of the thin film with the underlying carrier.
The non-rigid, non-planar characteristics of the thin film also cause localized areas of much higher pressure during gold compression bonding. Unlike semiconductor chips, thin films are not rigid structures. Accordingly, pressure applied to the thin film during gold compression bonding is not distributed evenly across the bonding area of the thin film. In addition, the non-planar nature of thin films also tends to cause formation of localized high-pressure points when the film is subjected to pressure.
Such localized pressures cause problems in two major ways. First, the localized pressure will often compress the thin-film interconnections. The thin-film connections extend beyond the intended connection region, creating non-optimal connections at best, and electrical short circuits in more extreme cases. Second, the actual localized pressure can far exceed the yield point of the thin film, damaging the thin film structure itself.
Module interconnection density is also impacted by the use of gold compression bonding. The joining areas of the opposing surfaces of the MLC and the thin film generally must be formed large enough to compensate for the lack of registration between the joining areas caused by the distortion and expansion of thin films from the temperature and pressure of gold compression bonding.
Mismatch of Thermal Coefficient of Expansion (TCE)
Semiconductor chips in many applications are attached to laminate substrates, such as printed circuit boards, rather than to MLC modules. A consistent obstacle in attaching chips to laminate substrates is the mismatch of the thermal coefficient of expansion, or TCE, between the chips and the laminated boards or substrates. This problem is especially acute in the case of direct chip attach. Direct chip attach, or DCA, is a growing trend in the microelectronics industry for many applications. Direct chip attach involves attaching semiconductors directly to a laminate substrate such as a printed circuit board or card.
The mismatch of TCE between chip and board generates shear stress on the chip-to-board connections; such shear stresses result in fatigue of the connections over the life of the product, making those connections prone to failure. In addition, the difference in TCE applies bending forces to the chips at their outer edges and, therefore, may cause the chip to crack.
One attempted solution to alleviate the problems caused by the difference in TCE is to interpose a ceramic carrier between the chip and the laminate board. The ceramic carrier has a TCE between the TCE of the board and that of the chip, thereby minimizing the stresses in the connections. The ceramic carrier also imparts increased rigidity to resist bending moments which would otherwise be applied to the chip. Unfortunately, the foregoing use of ceramic carriers complicates manufacturing and increases costs. The ceramic carrier is also relatively bulky in the context of microelectronics.
Another attempted compensation for the TCE mismatch is to use chip underfill between the chip and the board. Although such use of underfill reduces shear strain, continued presence of these forces limits chip sizes to only about 15 mm in the case of DCA and about 22 mm when the chip is attached to a ceramic substrate with associated underfill. In other words, even with underfill, there is simply too much stress on a chip when the chip dimensions exceed the dimensions mentioned above. This limitation on usable chip sizes is at odds with the ever-increasing size of chips currently being developed--a trend which is likely to continue in the future due to the demands of integrating a multitude of functions on a single chip.
Underfill also interferes with the ability to rework chips which fail testing. Failed chips that cannot be reworked must be discarded. Such waste is especially undesirable in the case of high-performance modules.
Need for Increased Wiring Density
A second problem related to increasing chip sizes is that larger chips are associated with increased wiring density requirements in the underlying substrate. For example, as the number of I/O connections increases, there is a correspondingly greater need for higher-density redistribution wiring. One approach to creating the required redistribution wiring is laminate packaging which uses surface laminar circuit or SLC technology. These types of substrates are produced by processing the basic laminate core panels through serial steps of dielectric and metal depositions and patterning. There are limits to this prior art technology; the basic ground rule (specifying minimum dimensions) for the lines on these build-up layers is two-mil lines with three-mil minimum spacing. The limitation associated with such a ground rule does not accommodate, however, the ever-increasing number of I/O connections and the corresponding need for higher-density redistribution wiring.
From the foregoing discussion, it may be seen that there is a need to process thin films without causing them to be damaged or distorted or to lose their registration with the areas to which they are to be connected. There is also a need to increase the amount of usable area of the thin film. There is a further need to improve the quality of active connections made between the thin film and the underlying carrier. There is a related need to prevent the interconnection structures from collapsing during processing. There is a still further need to accommodate increasing chip sizes by increasing the density of the wiring associated with laminate substrates while keeping stress, strain, and other undesirable forces from damaging the chip or fatiguing the connections to the chip.